Semiconductor devices are often manufactured by producing a plurality of layers disposed upon a substrate, such as a silicon wafer. The alignment between the various process layers is typically controlled to ensure proper functionality and performance of a resulting device. Misalignment between device features or structures formed within two or more successive layers is often referred to as overlay error. The ability to detect and correct overlay error between patterned layers on a wafer is critical to manufacture of integrated circuits and other semiconductor devices.
Overlay metrology is a known technique for determining misalignments or overlay error between patterned device layers, typically by analyzing an overlay “target” or “mark” disposed proximate to one or more device layers of interest. For example, overlay measurements may be performed via test patterns (i.e. one or more overlay target structures) printed together with various patterned device layers on a wafer. An overlay metrology system may include an imaging tool configured to collect image frames that are analyzed by a processing unit to determine a relative displacement or misalignment of the pattern elements making up device and target layers.
Typically, regions on a substrate are dedicated and used once for an overlay target. Sometimes an area can be used multiple times by double patterning (i.e. where one layer erases the other) or by inserting a metal grid or layer in between targets (in the Z direction). However, optical characteristics from previous target structures can interfere with subsequently printed target structures, and there are potential added material costs in the case of a metal grid or additional layer. As devices continue to be manufactured on smaller scales with more layers, it may be necessary to perform overlay measurements more often with an increased number of targets. Accordingly, space-saving techniques are needed in the art.